ECE Lab Report
In this experiment, we constructed a circuit that was connected to a 7-panel writing board. The 6 inputs from the circuit were hooked up to the corresponding pins on the XS40 FPGA board. Then 6 outputs from the corresponding pins on the XS40 FPGA board were then connected to a ribbon cable that was connected to a computer. When the circuit was complete, we wrote a program in C++ to interface the hardware with the PC using its parallel-I/O port. The program was then improved to implement a calculator interface and performed mathematical operations. There were 15 different combinations on writing panel, which corresponded to 10 different digits, 4 different operands, and an equal sign.Writing panel: it is consisted of 7 metallic panels. Each panel is soldered to a wire, which is connected to the D-latch. The writing panel is used for the user to input the combination of the corresponding number, operand, and equal sign.7474 D-latch: four chips were used during this lab because we need 7 inputs (Preset). Each panel from the writing board is connected to the PRE on the D-latch to set the state, '1' being used and '0' being unused. Three of four D-latches' CLRs were all connected to toget
One parsing problem was the issue of several digit numbers. When the 7 pad is touched, the number read from the computer's input port will be greater than 26=64. This configuration is simply to send inputs to the computer, where a calculator program is implemented. From measuring the voltage at each pin on the D-latches to check whether to chip was working to re-checking all the wire connections, we finally figured our problems. FLOW CHART:Flow Chart is on a separate piece of paper. It took 26% of the area using the first VHDL with the equations, and it took 47% of the area using the second VHDL,CONCLUSION: In conclusion, we have learned a great deal through trials and errors in completing this experiment. However, these problems were minor, but they took eternity find. SOFTWARE CODE: Software code is on a separate piece of paper. The last 4 bits were used to represent the different digits (1-9), operands (+, -, /, *) and '='. A continuous while loop constantly scans the input port for values, which are accepted as an unsigned short integer called Data Value. We used this to check whether the entered combination is legal or not, '1' being legal and '0' being illegal. When the subsequent operand is finished being entered, determined when the computer reads either another operator or the equal sign, the operation set by the flag is performed and the running total updated. Sending a momentary zero to Port B performs this reset. The input from the FPGA consists of 7 bits, one for each copper section on the writing pad. Therefore, I think in order to improve the quality and usage of the laboratory, the engineering department should send someone in once a week or twice a week to check on the equipments.
Common topics in this essay:
Data Value,
D-latches RESET,
XS40 FPGA,
VHDL CONCLUSION,
DESCRIPTION C++,
DESCRIPTION Writing,
RESET I/O,
,
D-latches' CLRs,
DISCUSSION CLR',
writing panel,
equal sign,
xs40 fpga board,
fpga board,
xs40 fpga,
running total,
input port,
separate piece paper,
6 bits,
flow chart,
paper software,
d-latches reset,
operand equal sign,
corresponding pins xs40,
pins xs40 fpga,
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Acceptance Essays
